PLDs are a well-known type of integrated circuit (IC) that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, digital clock managers (DCMs), Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of IC is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these ICs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Advancements in memory cell design have reduced the number of input/output (I/O) interfaces that are required to program, i.e., flip, the advanced memory cell. In particular, differential write memory cells have yielded to single-ended memory cells so as to significantly reduce the number of differential drivers required to configure the advanced memory cells. In addition, local reset circuitry has been removed from the advanced memory cells so as to further reduce I/O interface hardware and complexity within the memory cell.
Such I/O reductions, however, significantly increase the difficulties encountered when attempting to place the memory cell into a known logic state while the IC executes a power-up sequence. Providing additional logic pull-downs within the IC's repeater cells is insufficient, since the current magnitude drawn by a particular memory cell array may preclude a guaranteed logic state of the memory cell during a power-up sequence of the IC.
Efforts continue, therefore, to provide power-up circuitry and power-up sequences that allow the enhanced memory cells to be correctly biased to known logic states during initialization/power-up of the IC.